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INTEGRATED CIRCUITS
P82B96 Dual bi-directional bus buffer
Product data Supersedes data of 2003 Apr 02 2004 Mar 26
Philips Semiconductors
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
PIN CONFIGURATIONS 8-pin dual in-line, SO, TSSOP
Sx
1
8
VCC
Rx
2
7
Sy
Tx
3
6
Ry
FEATURES
* Bi-directional data transfer of I2C-bus signals * Isolates capacitance allowing 400 pF on Sx/Sy side and * Tx/Ty outputs have 60 mA sink capability for driving
4000 pF on Tx/Ty side low impedance or high capacitive buses
GND
4
5
Ty
SU01011
* Splits
side independent of supply voltage I2C
* Low power supply current * ESD protection exceeds 3500 V HBM per JESD22-A114,
signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need uni-directional input and output signal paths.
* Latch-up free (bipolar process with no latching structures) * Packages offered: DIP, SO, and TSSOP
TYPICAL APPLICATIONS
(e.g., 5 V and 3 V or 15 V)
250 V DIP package / 400 V SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101
* Interface between I2C buses operating at different logic levels * Interface between I2C and SMB (350 A) bus standard. * Simple conversion of I2C SDA or SCL signals to multi-drop * Interfaces with Opto-couplers to provide Opto isolation between
I2C-bus nodes up to 400 kHz. differential bus hardware, e.g., via compatible PCA82C250.
DESCRIPTION
The P82B96 is a bipolar IC that creates a non-latching, bi-directional, logic interface between the normal I2C-bus and a range of other bus configurations. It can interface I2C-bus logic signals to similar buses having different voltage and current levels. For example it can interface to the 350 A SMB bus, to 3.3 V logic devices, and to 15 V levels and/or low impedance lines to improve noise immunity on longer bus lengths. It achieves this interface without any restrictions on the normal I2C protocols or clock speed. The IC adds minimal loading to the I2C node, and loadings of the new bus or remote I2C nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bi-directional signal line with I2C properties. 2004 Mar 26 2
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SYMBOL Sx PIN 1 2 3 4 5 6 7 8 DESCRIPTION I2C-bus (SDA or SCL) Rx Tx Receive signal Transmit signal GND Ty Negative Supply Transmit signal Receive signal Ry Sy I2C-bus (SDA or SCL) Positive supply VCC SPECIAL NOTE: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bi-directional I2C signals do not allow any direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy to avoid latching of this buffer. A "regular I2C low" applied at the Rx/Ry of a P82B96 will be propagated to Sx/Sy as a "buffered low" with a slightly higher voltage level. If this special "buffered low" is applied to the Sx/Sy of another P82B96 that second P82B96 will not recognize it as a "regular I2C-bus low" and will not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended for, and compatible with, the normal I2C logic voltage levels of I2C master and slave chips--or even Tx/Rx signals of a second P82B96 if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C logic voltage levels of all I2C parts. There are NO restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave devices. For more details see Application Note AN255.
* 400 kHz operation over at least 20 meters of wire (see AN10148) * Supply voltage range of 2 V to 15 V with I2C logic levels on Sx/Sy
PINNING
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
ORDERING INFORMATION
PACKAGES 8-pin plastic dual In-line package 8-pin plastic small outline package 8-pin plastic thin shrink small outline package TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C ORDER CODE P82B96PN P82B96TD P82B96DP TOPSIDE MARK P82B96PN P82B96T 82B96 DRAWING NUMBER SOT97-1 SOT96-1 SOT505-1
NOTE: 1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
BLOCK DIAGRAM
+VCC (2-15 V)
8
Sx (SDA)
1
3
Tx (TxD, SDA)
2 Rx (RxD, SDA)
Sy (SCL)
7
5
Ty (TxD, SCL)
6
Ry (RxD, SCL)
P82B96
4
GND
SU01012
FUNCTIONAL DESCRIPTION
The P82B96 has two identical buffers allowing buffering of both of the I2C (SDA and SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the I2C interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the I2C-bus interface. Thus these paths are: 1. Sense the voltage state of the I2C pin Sx (or Sy) and transmit this state to the pin Tx (Ty resp.), and 2. Sense the state of the pin Rx (Ry) and pull the I2C pin LOW whenever Rx (Ry) is LOW. The rest of this discussion will address only the "x" side of the buffer: the "y" side is identical. The I2C pin (Sx) is designed to interface with a normal I2C-bus. are independent of The logic threshold voltage levels on the the IC supply VCC The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is 3 mA. The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC: with a typical switching threshold of half VCC. I2C-bus Tx is an open collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. A logic LOW is only transmitted to Tx when the voltage at the I2C pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in accordance with I2C requirements (max. 1.5 V in 5 V applications) but not low enough to be looped back to the Tx output and cause the buffer to latch LOW. The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically 0.8 V. If the supply voltage VCC fails, then neither the I2C nor the Tx output will be held LOW. Their open collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on Sx and Rx also present no loading of external signals even when VCC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 7 pF for all bus voltages and supply voltages including VCC = 0 V.
2004 Mar 26
3
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2004 Mar 26 dVSx/dT, dVSy/dT IRx, IRy IRx, IRy ISx, ISy ITx, ITy ITx, ITy ITx, ITy VTx, VTy ISx, ISy ISx, ISy ISx, ISy ISx, ISy ICC ICC ICC VCC Tamb Tstg Rtot I VRx VTx Vbus VSx, VSy VSx, VSy VSx, VSy SYMBOL At Tamb = 25 C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.
CHARACTERISTICS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages with respect to pin GND (pin 4).
MAXIMUM RATINGS
Philips Semiconductors
Output Logic LOW Levels
Input Currents
Bus pull-up (load) voltages and currents
Power Supply
VCC to GND
Dual bi-directional bus buffer
SYMBOL
Output logic level LOW, on normal I2C bus (Note 2)
Output logic level LOW, on normal I2C bus (Note 2)
Temperature coefficient of output LOW levels (Note 2)
Leakage current on buffered bus input
Input current from buffered bus
Input current from I2C-bus
Leakage current on buffered bus
Dynamic output sink capability, buffered bus
Static output loading on buffered bus
Maximum output voltage level
Leakage current on I2C-bus
Leakage current on I2C-bus
Dynamic output sink capability on I2C-bus
Static output loading on I2C-bus (Note 1)
Maximum input/output voltage level
Additional supply current per Tx or Ty LOW
Supply current at VCC = 15 V, buses HIGH
Supply current, buses HIGH
Supply voltage (operating)
Operating ambient temperature range
Storage temperature range
Power dissipation
DC current (any pin)
Voltage range on receive input
Voltage range on buffered output
Voltage range on I2C Bus, SDA or SCL
Supply voltage range VCC
PARAMETER
PARAMETER
ISx, ISy = 0.2 mA
ISx, ISy = 0.2 mA
ISx, ISy = 3 mA
VRx, VRy = VCC
bus LOW VRx, VRy = 0.4 V
bus LOW VRx, VRy = HIGH
VTx, VTy = VCC = 15 V; VSx, VSy = HIGH
VTx, VTy > 1 V VSx, VSy = LOW on I2C-bus = 0.4 V
VTx, VTy = 0.4 V; VSx, VSy = LOW on I2C-bus = 0.4 V
Open collector
VSx, VSy = 15 V; VRx, VRy = HIGH
VSx, VSy = 5 V; VRx, VRy = HIGH
VSx, VSy > 2 V; VRx, VRy = LOW
VSx, VSy = 1.0 V; VRx, VRy = LOW
Open collector; I2C-bus and VRx, VRy = HIGH
4
CONDITIONS
MIN.
670 0.8 0.2 2.0 60 -- -- -- -- -- -- -- -- -- -- -- -- 7
MIN.
-0.3
-0.3
-0.3
-0.3
--
-40
-55
--
--
TYP.
-1.8 0.88 730 100 1.7 1.1 0.9 -1 -1 18 -- -- -- -- -- -- 1 1 1
MAX.
+125
+85
+18
+18
+18
+18
300
250
MAX.
790 1.0 3.5 2.5 1.8 30 15 15 15 -- -- -- -- -- -- -- 1 3
--
P82B96
Product data
UNIT
mW
mV/K UNIT mA C C mV mA mA mA mA mA mA mA V V V V A A A A A A V V V V
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
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SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Input logic switching threshold voltages VSx, VSy VSx, VSy dVSx/dT, dVSy/dT Input logic voltage LOW (Note 3) On normal I2C-bus On normal I2C-bus -- -- 640 650 -2 -- -- 600 -- -- -- -- mV mV Input logic level HIGH threshold (Note 3) 700 Temperature coefficient of input thresholds Input logic HIGH level Input threshold Input logic LOW level mV/K V V V VRx, VRy VRx, VRy VRx, VRy VSx, VSy Fraction of applied VCC Fraction of applied VCC Fraction of applied VCC 0.58 -- -- 0.5 0.42 -- Logic level threshold difference Input/Output logic level difference (Note 1) VSX output LOW at 0.2 mA - VSX input HIGH max 50 85 mV NOTES: 1. The minimum value requirement for pull-up current, 200 A, guarantees that the minimum value for VSX output LOW will always exceed the minimum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute levels allow a small probability the LOW from one SX output is recognized by an SX input of another P82B96 this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes. 2. The output logic LOW depends on the sink current. For scaling, see Application Note AN255. 3. The input logic threshold is independent of the supply voltage.
CHARACTERISTICS
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SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Bus Release on VCC Failure VSx, VSy, VTx, VTy dV/dT VCC voltage at which all buses are guaranteed to be released -- -- -- 1 V Temperature coefficient of guaranteed release voltage -4 -- mV/K Buffer response time Tfall delay VSx to VTx VSy to VTy Trise delay VSx to VTx VSy to VTy Buffer time delay on FALLING input between VSx = input switching threshold, and VTx output falling 50%. Buffer time delay on RISING input between VSx = input switching threshold, and VTx output reaching 50% VCC RTx pull-up = 160 , no capacitive load, VCC = 5 V RTx pull-up = 160 , no capacitive load, VCC = 5 V RSx pull-up = 1500 , no capacitive load, VCC = 5 V -- 70 -- ns -- 90 -- ns Tfall delay VRx to VSx VRy to VSy Trise delay VRx to VSx VRy to VSy Buffer time delay on FALLING input between VRx = input switching threshold, and VSx output falling 50%. Buffer time delay on RISING input between VRx = input switching threshold, and VSx output reaching 50% VCC -- 250 -- ns RSx pull-up = 1500 , no capacitive load, VCC = 5 V -- 270 -- ns Input capacitance Cin Effective input capacitance of any signal pin measured by incremental bus rise times -- -- 7 pF NOTES ON RESPONSE TIME The fall-time of VTX from 5 V to 2.5 V in the test is approximately 15 ns. The fall-time of VSX from 5 V to 2.5 V in the test is approximately 50 ns. The rise-time of VTX from 0 V to 2.5 V in the test is approximately 20 ns. The rise-time of VSX from 0.9 V to 2.5 V in the test is approximately 70 ns. 2004 Mar 26 5
At Tamb = 25 C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
TYPICAL APPLICATIONS
See AN460 and AN255 for more application detail.
+VCC (2-15 V) +5 V R1 I2C SDA Tx (SDA) `SDA' (NEW LEVELS)
Rx (SDA) 1/2 PB2B96
SU01013
Figure 1. Interfacing an `I2C' type of bus with different logic levels.
+VCC1 R4 R2
+VCC
R5 R3 I2C SDA +5 V R1 I2C SDA Rx (SDA)
Tx (SDA)
1/2 P82B96
SU01014
Figure 2. Galvanic isolation of I2C nodes via opto-couplers
MAIN ENCLOSURE 12 V
REMOTE CONTROL ENCLOSURE 12 V
3.3-5 V LONG CABLES
3.3-5 V
SCL
SCL
3.3-5 V
12 V
3.3-5 V
SDA
SDA
P82B96
P82B96
SU01708
Figure 3. Long distance I2C communications
2004 Mar 26
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Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
VCC1 100 nF
+V CABLE DRIVE 100 k +V CABLE DRIVE VCC2 VCC BC 847B
VCC
RX SX TX
3 - 20 m CABLES
RX TX SX
SCL
SCL
I2C/DDC MASTER
RY I2C/DDC 4K7 RY TY SY
I2C/DDC SLAVE
SDA
SY
TY 470 k
SDA
P82B96
470 k
BC 847B
P82B96
GND MONITOR/FLAT TV
GND PC/TV RECEIVER/DECODER BOX R G B
su01785
VIDEO SIGNALS
Figure 4. Extending a DCC bus Figure 4 shows how a master I2C-bus can be protected against short circuits or failures in applications that involve plug/socket connections and long cables that may become damaged. A simple circuit is added to monitor the SDA bus and if its LOW time exceeds the design value then the master bus is disconnected. P82B96 will free all its I/Os if its supply is removed, so one option is to connect its VCC to the output of a logic gate from, say, the 74LVC family. The SDA and SCL lines could be timed and VCC disabled via the gate if one or other lines exceeds a design value of `LOW' period as in Figure 28 of AN255. If the supply voltage of logic gates restricts the choice of VCC supply then the low-cost discrete circuit in Figure 4 can be used. If the SDA line is held LOW, the 100 nF capacitor will charge and the Ry input will be pulled towards VCC. When it exceeds VCC/2 the Ry input will set the Sy input HIGH, which in practice means simply releasing it. In this example the SCL line is made uni-directional by tying the Rx pin to VCC. The state of the buffered SCL line cannot affect the master clock line which is allowed when clock-stretching is not required. It is simple to add an additional transistor or diode to control the Rx input in the same way as Ry when necessary. The +V cable drive can be any voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up resistors for a static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the connected devices. Because DDC uses relatively low speeds (<100 kHz), the cable length is not restricted to 20 m by the I2C signalling, but it may be limited by the video signalling. Figure 5 shows that P82B96 can achieve high clock rates over long cables. While calculating with lumped wiring capacitance yields reasonable approximations to actual timing, even 25 meters of cable 2004 Mar 26 7 is better treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer edge, will have a characteristic impedance in the range 100 - 200 . For simplicity they cannot be terminated in their characteristic impedance but a practical compromise is to use the minimum pull-up allowed for P82B96 and place half this termination at each end of the cable. When each pull-up is below 330 , the rising edge waveforms have their first voltage `step' level above the logic threshold at Rx and cable timing calculations can be based on the fast rise/fall times of resistive loading plus simple one-way propagation delays. When the pull-up is larger, but below 750 , the threshold at Rx will be crossed after one signal reflection. So at the sending end it is crossed after 2 times the one-way propagation delay and at the receiving end after 3 times that propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way propagation delays will be about 5 ns/meter. The 10% to 90% rise and fall times on the cable will be between 20 ns and 50 ns, so their delay contributions are small. There will be ringing on falling edges that can be damped, if required, using Schottky diodes as shown. When the Master SCL HIGH and LOW periods can be programmed separately, e.g. using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow for bus delays. The LOW period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave's response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master. Because the buffer will `stretch' the programmed SCL LOW period, the actual SCL
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
frequency will be lower than calculated from the programmed clock periods. In the example for 25 meters the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA rising edge is delayed 570 ns. The required additional LOW period is (490 + 570) = 1060 ns and the I2C-bus specifications already include an allowance for a worst case bus risetime 0 to 70% of 425 ns. (The bus risetime can be 300 ns 30% to 70%, which means it can be 425 ns 0-70%. The 25-meter cable delay times as quoted already include all rise/fall times.) Therefore, the micro only needs to be programmed with an addtional (1060 - 400 - 425) = 235 ns, making a total programmed LOW period 1535 ns. The programmed LOW will the be stretched by 400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
Note that in both the 100-meter and 250-meter examples the capacitive loading on the I2C-buses at each end is within the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of a `hybrid' mode because it relies on the response delays of Fast mode parts but uses (allowable) Standard mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large propagation delays so these systems need to operate well below the 400 kHz limit but illustrate how they can still exceed the 100 kHz limit provided all parts are capable of Fast mode operation. The fastest example illustrates how the 400 kHz limit can be exceeded provided master and slave parts have delay specifications smaller than the maximum allowed. Many Philips slaves have delays shorter than 600 ns, but none have that guaranteed.
+V CABLE DRIVE VCC1 R2 VCC R2 RX SCL SX TX R1 R1 R1 R1 RX TX SX SCL VCC2 R2 VCC R2
I2C MASTER
RY
RY
I2C SLAVE(S)
SDA
SY
TY CABLE
TY
SY
SDA
P82B96
P82B96
C2
C2
PROPAGATION DELAY ' 5 ns/m
C2
C2
GND BAT54A BAT54A
GND
su01786
Figure 5. Driving ribbon or flat telephone cables
EXAMPLES OF BUS CAPABILITY (refer to Figure 5)
+VCC CC1 +V CABLE +VCC CC2 R1 R2 C2 (pF) CABLE LENGTH CABLE CAPACITANCE CABLE DELAY SET MASTER NOMINAL SCL HIGH PERIOD 600 ns LOW PERIOD 4000 ns EFFECTIVE BUS CLOCK SPEED 120 kHz MAXIMUM SLAVE RESPONSE DELAY Normal spec. 400 kHz parts Normal spec. 400 kHz parts Normal spec. 400 kHz parts 600 ns
5V
12 V
5V
750
2.2 k
400
250 m
Not applicable (delay based) Not applicable (delay based)
1.25 s
5V
12 V
5V
750
2.2 k
220
100 m
500 ns
600 ns
2600 ns
185 kHz
3.3 V 3.3 V
5V 5V
3.3 V 3.3 V
330 330
1k 1k
220 100
25 m 3m
1 nF 120 pF
125 ns 15 ns
600 ns 600 ns
1500 ns 1000 ns
390 kHz 500 kHz
2004 Mar 26
8
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
CALCULATING SYSTEM DELAYS AND BUS CLOCK FREQUENCY FOR A FAST MODE SYSTEM
LOCAL MASTER BUS VCCM VCCB BUFFERED EXPANSION BUS REMOTE SLAVE BUS VCCS
Rm MASTER SCL
Rb
Rs SCL SLAVE
Sx
P82B96
Tx/Rx
Tx/Rx
P82B96
Sx
I2C
I2C
Cm = MASTER BUS CAPACITANCE GND/0 V A)
Cb = BUFFERED BUS WIRING CAPACITANCE
Cs = SLAVE BUS CAPACITANCE
FALLING EDGE OF SCL AT MASTER IS DELAYED BY THE BUFFERS AND BUS FALL TIMES C = F, V = VOLTS
EFFECTIVE DELAY OF SCL AT SLAVE = 255 + 17 VCCM + (2.5 + 4 x 109 Cb) VCCB (ns)
su01787
Figure 6.
LOCAL MASTER BUS VCCM VCCB BUFFERED EXPANSION BUS
MASTER
SCL
Rm
Rb
Sx
P82B96
Tx/Rx
Tx/Rx
I2C Cm = MASTER BUS CAPACITANCE GND/0 V Cb = BUFFERED BUS WIRING CAPACITANCE
B)
RISING EDGE OF SCL AT MASTER IS DELAYED (CLOCK STRETCH) BY BUFFER AND BUS RISE TIMES EFFECTIVE DELAY OF SCL AT MASTER = 270 + RmCm + 0.7RbCb (ns), C = F, R =
su01788
Figure 7.
2004 Mar 26
9
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
LOCAL MASTER BUS VCCM VCCB
BUFFERED EXPANSION BUS
REMOTE SLAVE BUS VCCS
Rm MASTER SDA
Rb
Rs SDA SLAVE
Sx
P82B96
Tx/Rx
Tx/Rx
P82B96
Sx
I2C
I2C
Cm = MASTER BUS CAPACITANCE GND/0 V C)
Cb = BUFFERED BUS WIRING CAPACITANCE
Cs = SLAVE BUS CAPACITANCE
RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES C = F, R =
EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns),
su01789
Figure 8. Figures 6, 7, and 8 show the P82B96 used to drive extended bus wiring, with relatively large capacitance, linking two Fast mode I2C-bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3/5 V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the actual bus frequency will be lower than the nominal Master timing due to bit-wise stretching of the clock periods. The delay factors involved in calculation of the allowed bus speed are: A) The propagation delay of the Master signal through the buffers and wiring to the Slave. The important delay is that of the falling edge of SCL because this edge `requests' the data or Acknowledge from a Slave. B) The effective stretching of the nominal LOW period of SCL at the Master caused by the buffer and bus rise times C) The propagation delay of the Slave's response signal through the buffers and wiring back to the Master. The important delay is that of a rising edge in the SDA signal. Rising edges are always slower and are therefore delayed by a longer time than falling edges. (The rising edges are limited by the passive pull-up while falling edges are actively driven) The timing requirement in any I2C system is that a Slave's data response (which is provided in response to a falling edge of SCL) must be received at the Master before the end of the corresponding low period of SCL as appears on the bus wiring at the Master. Since all Slaves will, as a minimum, satisfy the worst case timing requirements of a 400 kHz part, they must provide their response within the minimum allowed clock LOW period of 1300 ns. Therefore in systems that introduce additional delays it is only necessary to extend that minimum clock low period by any "effective" delay of the Slave's response. The effective delay of the slaves response = total delays in SCL falling edge from the Master reaching the Slave (A) - the effective delay (stretch) of the SCL rising edge (B) + total delays in the Slave's response data, carried on SDA, reaching the Master (C). The Master microcontroller should be programmed to produce a nominal SCL LOW period = (1300 + A - B + C) ns, and should be programmed to produce the nominal minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If found necessary, just increase either clock period. Due to clock stretching, the SCL cycle time will always be longer than (600 + 1300 + A + C) ns. Example: The Master bus has an RmCm product of 100 ns and VCCM = 5 V. The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus also has an RsCs product of 100 ns. The microcontroller LOW period should be programmed to (1300 + 372.5 - 482 + 472) ns, that is 1662.5 ns. Its HIGH period may be programmed to the minimum 600 ns. The nominal microcontroller clock period will be (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz. The actual bus clock period, including the 482 ns clock stretch effect, will be below (nominal + stretch) = (2262.5 + 482) ns or 2745 ns, equivalent to an allowable frequency of 364 kHz.
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Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
12 V
12 V TWISTED-PAIR TELEPHONE WIRES, USB, OR FLAT RIBBON CABLES. UP TO 15 V LOGIC LEVELS, INCLUDE VCC AND GND.
3.3-5 V TX SCL SX RX
3.3-5 V TY SDA SY RY
12 V
3.3 V
3.3 V
P82B96 P82B96 SX SY
P82B96 SX SY
P82B96 SX SY
P82B96 SY SDA SX SCL
SCL/SDA
SCL/SDA
SCL/SDA
NO LIMIT TO THE NUMBER OF CONNECTED BUS DEVICES.
su01709
Figure 9. I2C multi-point applications
ch1: freq = 624 kHz Tx 10 V
ch1: freq = 624 kHz Rx
Sx Sx 5V
0V CH1!2.00V = AVG CH2!2.00V = BWL MTB 200 ns - 0.98dvch1+ Horiz: 200 ns/div. VertL 2 V/div. CH1!2.00V = AVG CH2!2.00V = BWL MTB 200 ns - 0.98dvch1+
SU01069
Horiz: 200 ns/div. VertL 2 V/div.
SU01070
Figure 10. Propagation Sx to Tx -- Sx pull-up to 5V, Tx pull-up to VCC = 10 V
Figure 11. Propagation Rx to Sx -- Sx pull-up to 5V, Rx pull-up to VCC = 10 V
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11
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2004 Mar 26
12
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
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13
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
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Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
REVISION HISTORY
Rev _4 Date 20040326 Description Product data (9397 750 12932). Supersedes data of 2003 Apr 02 (9397 750 11351). Modifications:
* Page 2:
- Features section re-written. - Add "TSSOP" to heading for pin configurations
* Page 3, Ordering information table: correct description of TSSOP8 package. * Page 5, (continued) Characteristics table, Note 1,
- third sentence: from "... the LOW from on SX output ..." to "... the LOW from one SX output ..." - fourth sentence: from "In any design the SX pins of different ICs because the resulting ..." to "In any design the SX pins of different ICs should never be linked because the resulting ..." and VCC to indicate optional/allowed links.
* Figure 4: Change 2 transistors to bipolar type. Add dashed line between VCC1 and VCC, and between VCC2 * Figure 5: Add dashed line between VCC1 and VCC, and between VCC2 and VCC to indicate optional/allowed * Page 8, table "Examples of bus capability":
- cable capacitance 1 nF: change LOW period from "1600 ns" to "1500 ns" change Effective bus clock speed from "380 kHz" to "390 kHz" - change cable capacitance "120 nF" to "120 pF" links.
* Add title "Calculating system delays and bus clock frequency for a Fast mode system" on page 9. * Add VCCB label to Figures 6, 7 and 8. * Page 10, "Example:" paragraphs 3, 5 and 6: values corrected in equations. * Add signal names to Figure 9. * Add package outline drawing SOT505-1.
_3 _2 _1 20030402 20030226 20010306 Product data (9397 750 11351); ECN 853-2241 29602 dated 28 February 2003. Supersedes data of 2003 Jan 22 (9397 750 11093) Product data (9397 750 11093); ECN 853-2241 29410 of 22 January 2003; supersedes data of 2001 Mar 06 (9397 750 08122) Product data (9397 750 08122); ECN 853-2241 25758 of 2001 Mar 06.
2004 Mar 26
15
Philips Semiconductors
Product data
Dual bi-directional bus buffer
P82B96
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 03-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 12932
Philips Semiconductors
2004 Mar 26 16

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